1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an interlayer insulating film suitable for electrically insulating metal wiring layers such as an aluminum layer from other layers, and a method of fabricating the same.
2. Description of the Related Art
As a semiconductor device has been fabricated smaller and smaller in size, it is not avoidable to adopt a multi-layer wiring in a structure of a semiconductor device. An insulating layer made of silicon dioxide has been employed as an interlayer insulating film for a semiconductor device having a multi-layer wiring structure. With a semiconductor device having been fabricated in a higher density, there arises a problem that a semiconductor device cannot operate at a higher operation speed because of signal delay caused by parasitic capacitance between wirings. A conventionally used silicon dioxide film has a dielectric constant of about 3.9 at smallest, and thus it is expected to develop an insulating layer having a lower dielectric constant.
There is another problem that if there is a large irregularity on a surface of an interlayer insulating film, a resist pattern cannot be formed because of shortage of the focusing margin in a photolithography step for formation of an upper wiring layer, and that even if a resist pattern could be formed, an upper wiring layer might be broken at a large irregularity of an underlying interlayer insulating film, and a portion of material of which a wiring layer is made would not be etched out and would remain as residue. For these reasons, an interlayer insulating film is required to have a flat surface. As a semiconductor device is fabricated in a higher density, an exposure device having a higher numerical aperture is employed in a photolithography step in order to form a more fine wiring, in which case there will arise a problem of a decreased focusing margin. Thus, an interlayer insulating film is required to have a flat surface across the chip size.
In brief, an interlayer insulating film to be used for a highly integrated semiconductor device having a multi-layer wiring structure is required to have a low dielectric constant for filling a space formed between wirings therewith, and to have a flat surface across the chip size.
Recently, an attempt of adding fluorine (F) into a silicon dioxide film for lowering a dielectric constant has drawn attention. For instance, one of methods of making a fluorine containing silicon dioxide film has been suggested in the abstract of International Conference on Solid State Device and Materials, pp. 161-163, 1993. A conventional parallel plate type plasma-enhanced chemical vapor deposition apparatus is employed as a film making apparatus, and tetra ethyl ortho silicate (hereinafter, referred to simply as "TEOS"), C.sub.2 F.sub.6 and oxygen (O.sub.2) are used as materials from which the film is made. According to the abstract, a dielectric constant of an interlayer insulating film is reduced down to about 3.7 with an increase of an amount of C.sub.2 F.sub.6.
Another method of making a fluorine containing interlayer insulating film has been suggested in an article found in SEMI Technology Symposium prepublished booklet, pp. 179-185, 1994. This method employs the same apparatus as the above mentioned, but gas species as a fluorine addition agent are varied for making a film. The article analyzed three gas species; NF.sub.3, CF.sub.4 and C.sub.2 F.sub.6. The article stated that the employment of C.sub.2 F.sub.6 reduced a dielectric constant of the film down to 3.4. In general, a dielectric constant is reduced with an increase in an amount of fluorine to be added to an interlayer insulating film.
As an alternative, chemical mechanical polishing (hereinafter, referred to simply as "CMP") has attracted attention these days as a process for planarizing a surface of an interlayer insulating film at a chip size. For instance, Japanese Unexamined Patent Publication No. 6-283485 has suggested a method of fabricating a semiconductor device in which method CMP is performed on a fluorine containing silicon dioxide film. Hereinbelow is explained the method.
First, as illustrated in FIG. 1A, there is formed an insulating film 2 made of silicon dioxide on a silicon substrate 1. Then, a patterned lower wiring layer 3 made of metal such as aluminum is formed on the insulating film 2. Then, as illustrated in FIG. 1B, there is formed a fluorine containing silicon dioxide film 4 on the lower wiring layer 3 and the insulating film 2 by plasma-enhanced chemical vapor deposition (hereinafter, referred to simply as "PECVD") employing TEOS gas to which NF.sub.3 is added. Then, as illustrated in FIG. 1C, there is deposited a silicon dioxide film 5 containing no fluorine on the fluorine containing silicon dioxide film 4 so that the silicon dioxide film 5 containing no fluorine has a top surface higher than a top surface of the lower wiring layer 3.
Then, as illustrated in FIG. 1D, the no fluorine containing silicon dioxide film 5 is polished by CMP until a top surface of the fluorine containing silicon dioxide film 4 appears. In CMP, since the fluorine containing silicon dioxide film 4 has a lower polishing rate than that of the no fluorine containing silicon dioxide film 5, the fluorine containing silicon dioxide film 4 has a function of a stopper for CMP. Specifically, when the fluorine containing silicon dioxide film 4 begins to be polished, the polishing speed seems to decrease to zero. Thus, the polishing of the no fluorine containing silicon dioxide film 5 is stopped when a top surface of the fluorine containing silicon dioxide film 4 appears, resulting in that the no fluorine containing silicon dioxide film 5 has a top surface nearly on a level with a top surface of the fluorine containing silicon dioxide film 4.
Then, as illustrated in FIG. 1E, a via hole 6 is formed in communication with the lower wiring layer 3 by means of photolithography, wet etching and dry etching. Then, as illustrated in FIG. 1F, an upper wiring layer 7 made of metal such as aluminum is formed by sputtering, photolithography and dry etching so that the upper wiring layer 7 covers a resultant therewith.
Another method of CMP using a stopper has been suggested in Japanese Unexamined Patent Publication No. 6-326065. In this method, layers made of soft polishing material and layers made of hard polishing material are alternately deposited, and flatness of an interlayer insulating film is improved by utilizing a difference between polishing rates of the soft and hard materials. Hereinbelow is explained the method in detail.
As illustrated in FIG. 2A, there is formed an insulating film 10 on a silicon substrate 9. Then, a patterned lower wiring layer 11 made of metal such as aluminum is formed on the insulating film 10. Then, as illustrated in FIG. 2B, there is formed an interlayer insulating film 12 covering the lower wiring layer 11 and the insulating film 10 therewith. Then, over the interlayer insulating film 12 are deposited a hard polishing material layer 13a, a soft polishing material layer 14 and a hard polishing material layer 13b in this order. The lower hard polishing -material layer 13a acts as a polishing stopper for prevention of over-polishing to thereby enhance planarization of an interlayer insulating layer.
Then, as illustrated in FIG. 2C, portions of both the hard polishing material layer 13b and the soft polishing material layer 14 located above the lower wiring layer 11 are removed by CMP. That is, the hard polishing material layer 13b and the soft polishing material layer 14 are chemically and mechanically polished until a top surface of the lower hard polishing material layer 13a located above the lower wiring layer 11 appears. Portions 13bb of the upper hard polishing material layer 13b located between the patterned lower wiring layers 11 are not removed even by CMP, but it cooperates with portions 13aa of the lower hard polishing material layer 13a located above the lower wiring layers 11 to form a continuous planarized top surface.
Then, as illustrated in FIG. 2D, the portions 13bb of the upper hard polishing material layer 13b are removed by polishing or wet etching. Thus, portions 14a of the soft polishing material layer 14 located between the patterned lower wiring layers 11 and the portions 13aa of the lower hard polishing material layer 13a cooperate with each other to form a continuous, planarized top surface.
However, the above firstly mentioned method suggested in Japanese Unexamined Patent Publication No. 6-283485 has problems as follows.
The first problem is that if the fluorine containing silicon dioxide film 4 contains fluorine at a high concentration, the upper wiring layer 7 corrodes where it makes direct contact with the fluorine containing silicon dioxide film 4 with the result of formation voids 16 at an interface between the fluorine containing silicon dioxide film 4 and the upper wiring layer 7, as illustrated in FIG. 1F. In particular, where the upper wiring layer 7 made of aluminum makes direct contact with the fluorine containing silicon dioxide film 4 within the via hole 6, the upper wiring layer 7 is attenuated due to corrosion to thereby have a tendency of being readily broken.
The reason is that if fluorine makes a direct bond with silicon, such Si-F bonding is stable, however, if fluorine makes insufficient bond with silicon, hydrolysis will readily take place due to moisture in the air, and hence hydrogen fluoride (HF) is produced. In particular, if the fluorine containing silicon dioxide film 4 had a low density and was porous, cubical expansion thereof will readily take place because of hydrolysis thereof, resulting in hydrogen fluoride (HF) being readily produced.
The second problem is that a fluorine containing silicon dioxide film has a lower polishing rate than a polishing rate of a no fluorine containing silicon dioxide film in CMP.
The reason is as follows. A generally used slurry for CMP is aqueous solution including silica (SiO.sub.2) as abrasive particles and potassium hydroxide (KOH) as dispersion medium. The solution kept at a pH value at 11 or greater. Particles of a polished silicon dioxide film are dissolved into the solution for removal. Thus, while a fluorine containing silicon dioxide film is polished, fluorine is released out of the fluorine containing silicon dioxide film to thereby reduce the pH value of the solution. Hence, the polishing rate of the fluorine containing silicon dioxide film is reduced.
The third problem is that there are produced voids 17, as illustrated in FIG. 1B. The reason of the production of the voids 17 is that reaction takes place mainly in gas phase because oxidation of TEOS is facilitated due to addition of fluorine, and also because a pressure is high, specifically 1 Torr or higher, due to the use of a parallel plate type PECVD apparatus with the result that a shape of the fluorine containing silicon dioxide film 4 is deteriorated.
The fourth problem is that if an amount of fluorine source gas is increased for lowering the dielectric constant, there are formed cavities 18 on a surface of the insulating film 2, as illustrated in FIG. 1B.
The reason is as follows. As fluorine source gas, CF.sub.4 and/or C.sub.2 F.sub.6 gases are used. However, these gases are originally etching gases to be used for etching SiO.sub.2, and an etching rate of those gases is further increased in the presence of oxygen (O.sub.2). Thus, if an amount of CF.sub.4 and/or C.sub.2 F.sub.6 gases relative to an amount of TEOS is increased in order to lower a dielectric constant, the underlying insulating film 2 is first etched before the fluorine containing silicon dioxide film 4 is deposited on the insulating film 2.
The secondly mentioned method suggested in Japanese Unexamined Patent Publication No. 6-326065 has also problems as follows.
The first problem in the secondly mentioned method is that if either the hard polishing material layers 13a, 13b or the soft polishing material layer 14 is composed of a fluorine containing silicon dioxide film, an aluminum wiring layer such as an upper wiring layer is corroded at a via hole or a place where an aluminum wiring layer makes direct contact with a fluorine containing silicon dioxide film for the same reason as that of the first problem of the firstly mentioned Publication. In the case that an interlayer insulating film is composed of a fluorine containing silicon dioxide film, corrosion would take place in an aluminum layer for the same reason as mentioned above.
The second problem is that it is not possible to have a semiconductor device operated at a higher operation speed, a space between wirings is quite small. The reason is as follows. Even if either an interlayer insulating film, a hard polishing material layer or a soft polishing material layer is composed of a film having a low dielectric constant, it is quite small in volume. Thus, the use of a low dielectric constant film does not provide much advantage.